Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device employing buried gates (BG).
As semiconductor devices become miniaturized, achieving diverse device characteristics and performing appropriate processes have been gradually more difficult. Particularly, in achieving under 40 nm process technologies, physical limitations in terms of gate structure, bit line structure, and contact structure are being met. While a structure with such physical dimensions can be formed, it has been difficult to acquire satisfactory device characteristics, such as resistance, refresh, low failure, and breakdown voltage. In light of such a concern, a buried gate (BG) process in which gates are buried in active regions has been developed. The buried gate process decreases parasitic capacitance, increases process margins, and forms miniaturized cell transistors.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for fabricating a semiconductor device employing buried gates. FIGS. 2A to 2D are pictures illustrating a concern raised in a conventional semiconductor device employing buried gates.
Referring to FIG. 1A, a sealing layer 15 and an insulation layer 16 are sequentially formed over a substrate 11 including cell regions CELL, each cell region having a plurality of buried gates 100, and peripheral regions PERI. Herein, each of the buried gates 100 formed in the cell regions includes trenches 12, a cell gate insulation layer 13 formed on the surface of the trenches 12, and a cell gate electrode 14 filling a portion of the trench 12 over the cell gate insulation layer 13. The sealing layer 15 covers the profile of the substrate 11 while filling the other portion of the trench 12.
Subsequently, a bit line contact hole 17 is formed to expose the substrate 11 between the buried gates 100 by selectively etching the insulation layer 16 and the sealing layer 15 in each cell region. Then, a plug conductive layer 18 is deposited over the substrate 11 to fill the bit line contact hole 17.
Subsequently, a first photoresist pattern 19 is formed over the plug conductive layer 18 by using a peripheral open mask, and the plug conductive layer 18, the insulation layer 16, and the sealing layer 15 are sequentially etched using the first photoresist pattern 19 as an etch barrier, to thereby expose the substrate 11 in each peripheral region.
Referring to FIG. 1B, after the first photoresist pattern 19 is removed, a peripheral gate insulation layer 20 and a peripheral gate conductive layer 21 are sequentially formed over the substrate 11.
Subsequently, a second photoresist pattern 22 is formed over the peripheral gate conductive layer 21 by using a cell open mask. Herein, the linewidth W2 of the second photoresist pattern 22 is longer than the line width W1 of a predetermined peripheral region. This is to protect a structure formed at the boundary between the cell region and the peripheral region from being damaged by misalignment in a subsequent process.
Referring to FIG. 1C, a bit line contact plug 18A is formed by using the second photoresist pattern 22 as an etch barrier and sequentially etching the peripheral gate conductive layer 21, the peripheral gate insulation layer 20, and the plug conductive layer 18 in the cell region. After the formation of the bit line contact plug 18A, the second photoresist pattern 22 is removed. Hereafter, the etched peripheral gate conductive layer 21 is denoted with a reference numeral ‘21A’ and referred to as a peripheral gate conductive layer pattern 21A.
Herein, the step height between the cell region and the peripheral region and the second photoresist pattern 22 formed to have a longer linewidth W2 than the predetermined linewidth W1 of the peripheral region forms a protrusion A formed at the boundary between the cell region and the peripheral region after the etch process.
Referring to FIG. 1D, a planarization process is performed to remove the protrusion A formed at the boundary between the cell region and the peripheral region after the etch process. The planarization process may be performed using chemical mechanical polishing (CMP). Hereafter, the peripheral gate conductive layer pattern 21A with the protrusion A removed is denoted with a reference numeral ‘21B’ and referred to as “a protrusion-free peripheral gate conductive layer pattern 21B.”
Referring to FIG. 1E, a conductive layer 23 and a hard mask layer 24 are sequentially formed over the substrate 11. The hard mask layer 24, the conductive layer 23 and the insulation layer 16 in the cell region are sequentially etched to thereby form a bit line 26 contacting the bit line contact plug 18A, while the hard mask layer 24, the conductive layer 23, the protrusion-free peripheral gate conductive layer pattern 21B, and the peripheral gate insulation layer 20 in the peripheral region are sequentially etched to thereby form a peripheral gate 25. Hereafter, the etched protrusion-free peripheral gate conductive layer pattern 21B and the etched peripheral gate insulation layer 20 are denoted with reference numerals ‘21C’ and ‘20A’ and referred to as re-etched protrusion-free peripheral gate conductive layer pattern 21C and the peripheral gate insulation layer pattern 20A, respectively.
However, since the conventional technology forms the re-etched protrusion-free peripheral gate conductive layer pattern 21C after the formation of the plug conductive layer 18, it requires an etch process performed using a peripheral open mask to secure a space for forming the re-etched protrusion-free peripheral gate conductive layer pattern 21C and an etch process performed using a cell open mask to form the bit line contact plug 18A. Therefore, the conventional technology is relatively complicated and raises a concern in that the protrusion A is formed at the boundary between the cell region and the peripheral region.
Also, there is a concern in that a structure pre-formed in the cell region and the peripheral region are damaged during the planarization process which is performed to remove the protrusion A formed at the boundary between the cell region and the peripheral region. More specifically, the structure formed under the protrusion A may be dug out (see reference symbol ‘B’ in FIGS. 1D and 2) or the protrusion-free peripheral gate conductive layer pattern 21B in the peripheral region may be lost (see reference symbol ‘C’ in FIGS. 1D and 2B) as the protrusion A is removed during the planarization process. In FIGS. 2B, “poly” represents the peripheral gate conductive layer and “TEOS” represents the insulation layer.
As described above, the defects occurring during the planarization process performed to remove the protrusion A also raises a concern such as loss of the substrate 11 (see reference symbol ‘D’ in FIGS. 1E, 2C and 2D) during a subsequent process for forming the peripheral gate 25, thus deteriorating the characteristics and reliability of a semiconductor device.